Anna University Chennai
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010
Fourth Semester (R-2008) / 3rd Semester in R-2013
Electrical and Electronics Engineering
EE 2255 — DIGITAL LOGIC CIRCUITS
(Regulation 2008)
Time : Three hours Maximum : 100 Marks
Answer ALL questions
[ Note: New Subject Code in R-2013 is EE6301 ]
PART A — (10 × 2 = 20 Marks)
1. Show that Excess-3 code is self complementing.
2. Add the hexadecimal numbers: 93 and DE.
3. Convert JK flip-flop to T-flip-flop.
4. Mention the major application of Master Slave FF.
5. Draw the state diagram of SR Flip Flop.
6. Define asynchronous sequential machine.
7. State the important characteristics of TTL family.
8. In which type of TTL gate wired ANS logic is possible?
9. Write the VHDL code for AND gate.
10. List the operators available in VHDL.
PART B — (5 × 16 = 80 Marks)
11. (a) Reduce the following using tabulation method and verify with K maps.
( ) ( ) ∑ = 14 , 12 , 10 , 8 , 6 , 4 , 3 , 2 , 1 , 0 , , , D C B A F
Or
(b) Obtain the minimum SOP using Quine Mcclusky’s method and verify using ‘K’ map for the following.
13 12 11 10 9 8 4 2 0
m m m m m m m m m F + + + + + + + + = .
12. (a) Design a counter with the sequence 0, 1, 3, 7, 6, 4, 0.
Or
(b) The following sequence is to be realized by a counter consisting of 3 JKFF’s.
A1 0 0 0 0 1 1 0
A2 0 1 1 0 0 1 0
A3 0 1 0 1 1 0 0
Design the counter.
13. (a) (i) List and explain the steps used for analyzing an asynchronous sequential circuit. (8)
(ii) Describe procedure to get state table from excitation table in an asynchronous sequential circuit. How does it differ from synchronous sequential circuit? (8)
Or
(b) (i) How do you get output specifications from a flow table in asynchronous sequential circuit operating in fundamental mode? (6)
(ii) When do you get the critical and non-critical races? How will you obtain race free conditions (10)
14. (a) (i) Explain the concept, working and characteristics of TTL logic families. (8)
(ii) What do you understand by FPGA? Explain the operation and applications? (8)
Or
(b) (i) Describe the working of EPROM. List the applications of EPROM. (8)
(ii) Discuss on the concept, operation and characteristics of CMOS technology. (8)
15. (a) Construct a VHDL module listing for a 16:1 MUX that is based on the assign statement. Use a 4-bit select word S3 S2 S1 S0 to map the selected input Pi (i = 0,...15) to the output.
Or
(b) (i) Explain the design procedure of RTL using VHDL. (10)
(ii) Write a note on VHDL test benches. (6)
B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010
Fourth Semester (R-2008) / 3rd Semester in R-2013
Electrical and Electronics Engineering
EE 2255 — DIGITAL LOGIC CIRCUITS
(Regulation 2008)
Time : Three hours Maximum : 100 Marks
Answer ALL questions
[ Note: New Subject Code in R-2013 is EE6301 ]
PART A — (10 × 2 = 20 Marks)
1. Show that Excess-3 code is self complementing.
2. Add the hexadecimal numbers: 93 and DE.
3. Convert JK flip-flop to T-flip-flop.
4. Mention the major application of Master Slave FF.
5. Draw the state diagram of SR Flip Flop.
6. Define asynchronous sequential machine.
7. State the important characteristics of TTL family.
8. In which type of TTL gate wired ANS logic is possible?
9. Write the VHDL code for AND gate.
10. List the operators available in VHDL.
PART B — (5 × 16 = 80 Marks)
11. (a) Reduce the following using tabulation method and verify with K maps.
( ) ( ) ∑ = 14 , 12 , 10 , 8 , 6 , 4 , 3 , 2 , 1 , 0 , , , D C B A F
Or
(b) Obtain the minimum SOP using Quine Mcclusky’s method and verify using ‘K’ map for the following.
13 12 11 10 9 8 4 2 0
m m m m m m m m m F + + + + + + + + = .
12. (a) Design a counter with the sequence 0, 1, 3, 7, 6, 4, 0.
Or
(b) The following sequence is to be realized by a counter consisting of 3 JKFF’s.
A1 0 0 0 0 1 1 0
A2 0 1 1 0 0 1 0
A3 0 1 0 1 1 0 0
Design the counter.
13. (a) (i) List and explain the steps used for analyzing an asynchronous sequential circuit. (8)
(ii) Describe procedure to get state table from excitation table in an asynchronous sequential circuit. How does it differ from synchronous sequential circuit? (8)
Or
(b) (i) How do you get output specifications from a flow table in asynchronous sequential circuit operating in fundamental mode? (6)
(ii) When do you get the critical and non-critical races? How will you obtain race free conditions (10)
14. (a) (i) Explain the concept, working and characteristics of TTL logic families. (8)
(ii) What do you understand by FPGA? Explain the operation and applications? (8)
Or
(b) (i) Describe the working of EPROM. List the applications of EPROM. (8)
(ii) Discuss on the concept, operation and characteristics of CMOS technology. (8)
15. (a) Construct a VHDL module listing for a 16:1 MUX that is based on the assign statement. Use a 4-bit select word S3 S2 S1 S0 to map the selected input Pi (i = 0,...15) to the output.
Or
(b) (i) Explain the design procedure of RTL using VHDL. (10)
(ii) Write a note on VHDL test benches. (6)
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