The following question paper is the next set (set 2) of JNTU, Kakinada question paper for B.E CSE 2011, the subject Advanced Computer Architecture (First Semester). Get it now!
1. a) The trends in computer Technology indicate that bandwidth improves much more rapidly than latency. Substantiate.
b) Describe seven dimensions of an instruction set architecture.
c) What is the role of bench suites in measuring the performance of computer systems.
2. a) What is instruction level parallelism? What are the major hurdles of pipelining? Explain.
b) What are the critical goals in the instruction set, primarily, from the compiler view point?
3. a) Describe the advanced techniques for instruction delivery and speculation in pipelining.
b) How to overcome data hazards with dynamic scheduling? Explain.
4. a) Give the summery of at least 8 advanced cache optimizations showing the impact on cache performance and complexity.
b) Describe the architecture support for protecting process from each other via virtual memory?
5. a) Describe VLIW approach for branch projection in pipelining.
b) Differentiate between dynamic and static scheduling in ILP.
6. Describe synchronization mechanisms in multi processor systems.
7. Summarize the six stand RAID levels, with their fault tolerance and overhead in redundant disks.
8. Write short notes on two of the following.
a) Practical issues in inter connection networks
b) Bench marking of a storage device
c) Designing a cluster
Jawaharlal Nehru Technological University, Kakinada
Sub Code: M0523, Set: 02
Sub Code: M0523, Set: 02
IV B.Tech I Semester Regular Examinations, November, 2011
ADVANCED COMPUTER ARCHITECTURE
(Computer Science & Engineering)
Time: 3 hours Max. Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. a) The trends in computer Technology indicate that bandwidth improves much more rapidly than latency. Substantiate.
b) Describe seven dimensions of an instruction set architecture.
c) What is the role of bench suites in measuring the performance of computer systems.
2. a) What is instruction level parallelism? What are the major hurdles of pipelining? Explain.
b) What are the critical goals in the instruction set, primarily, from the compiler view point?
3. a) Describe the advanced techniques for instruction delivery and speculation in pipelining.
b) How to overcome data hazards with dynamic scheduling? Explain.
4. a) Give the summery of at least 8 advanced cache optimizations showing the impact on cache performance and complexity.
b) Describe the architecture support for protecting process from each other via virtual memory?
5. a) Describe VLIW approach for branch projection in pipelining.
b) Differentiate between dynamic and static scheduling in ILP.
6. Describe synchronization mechanisms in multi processor systems.
7. Summarize the six stand RAID levels, with their fault tolerance and overhead in redundant disks.
8. Write short notes on two of the following.
a) Practical issues in inter connection networks
b) Bench marking of a storage device
c) Designing a cluster
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