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Thursday, October 20, 2016

CS2253 Computer Organization and Architecture Nov Dec 2010 Question Paper

Anna University Chennai
B.E/B.Tech. DEGREE EXAMINATION, Nov Dec 2010
Question Paper Code: 10265
Computer Science and Engineering
Common to Information Technology
CS2253 Computer Organization and Architecture
(Regulation 2008)
03rd Semester in R-2013 / 04th Semester in R-2008
Time : Three hours
Maximum : 100 marks

Note: New Subject Code in R-2013 is CS6303

PART A — (10 × 2 = 20 Marks)

1. What does the term hertz refer to?

2. How is the number 25 represented in BCD and ASCII code?

3. What is mono phase?

4. What are the two possible error conditions that may arise in a stack operation?

5. How can memory access be made faster in a pipelined operation? Which hazards can be reduced by faster memory access?

6. How do you calculate the execution time T of a program that has a dynamic instruction count N?

7. What is memory interleaving?

8. How is disk access time calculated?

9. What are Priority groups?

10. What are the operating system routines of a keyboard driver?


PART B — (5 × 16 = 80 Marks)

11. (a) (i) Describe the connections between the processor and memory with a neat structure diagram. (Marks 8)

(ii) X=A X B + C X C (Marks 8)

Explain how the above expression will be executed in one address, two address and three address processors in an accumulator organization.

Or

(b) Explain in detail how Instructions are encoded. (Marks 16)

12. (a) (i) Draw the diagram of the single Bus Organization of the data path inside a processor. (Marks 8)

(ii) Explain the above regarding execution. (Marks 8)

Or

(b) (i) Explain the Organization of the control unit to allow conditional branching in the microprogram. (Marks 8)

(ii) How is a functional field micro instruction generated? Explain. (Marks 8)

 13. (a) Explain how the instruction pipeline works. What are the various situations where an instruction pipeline can stall? What can be its resolution? (Marks 16)

Or

(b) (i) Examine the relationships between pipeline execution and addressing modes. (Marks 8)

(ii) What do you mean by out of order execution? (Marks 8)


14. (a) Write a note on Asynchronous and Synchronous DRAMs. (Marks 16)

Or

(b) (i) Analyze the memory hierarchy in terms of speed, size and Cost. (Marks 8)

(ii) Explain the Address Translation in Virtual Memory. (Marks 8)

 15. (a) Explain the following:

(i) Memory mapped I/O (Marks 4)

(ii) I/O Registers (Marks 4)

(iii) Hardware Interrupts (Marks 4)

(iv) Vectored interrupt (Marks 4)

Or

(b) Write a note on SCSI BUS. Explain with a neat diagram.

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